1. Field of the Invention
The present invention relates to a memory device that utilizes single-poly electrically-programmable read-only-memory (EPROM) cells and, more particularly, to a memory device that utilizes single-poly EPROM cells which are programmed with CMOS compatible voltages.
2. Description of the Related Art
In the early 1970s, an electrically-programmable read-only-memory (EPROM) transistor based on a p-channel MOS device with a completely isolated gate was introduced by D. Frohmann-Bentchkowsky (see "A Fully Decoded 2048-bit Electrically Programmable MOS-ROM", IEEE ISSCC Digest of Technical Papers, p.80, 1971).
FIG. 1 shows a cross-sectional view that illustrates a Frohmann-Bentchkowsky memory transistor 10. As shown in FIG. 1, memory transistor 10 includes spaced-apart p-type source and drain regions 16 and 18, respectively, which are formed in an n-type well 14 which, in turn, is formed in a p-type substrate 12. (Source and drain regions 16 and 18 may alternately be formed in an n-type substrate).
In addition, transistor 10 also includes a channel region 20 which is defined between source and drain regions 16 and 18, and a layer of gate oxide 22 which is formed over channel region 20. Transistor 10 further includes a gate 24 which is formed over gate oxide layer 22, and a layer of insulation material 26 which, along with gate oxide layer 22, completely encapsulates gate 24. Since gate 24 is completely isolated, it is commonly referred to as a floating gate.
In operation, transistor 10 is programmed by applying biasing voltages to well 14 and drain 18 which are sufficient to induce avalanche breakdown. For example, avalanche breakdown is induced by applying ground to well 14 and a negative breakdown voltage to drain region 18 (while either grounding or floating source region 16), or by applying a positive breakdown voltage to well 14 and ground to drain region 18 (while floating or applying the positive breakdown voltage to source region 16).
The biasing voltages which are sufficient to induce avalanche breakdown establish a strong electric field across the drain-to-well junction depletion region. The strong junction electric field accelerates electrons in the junction depletion region (which are formed from thermally-generated electron-hole pairs) into hot electrons which then have ionizing collisions with the lattice, thereby forming "substrate hot electrons".
A number of these substrate hot electrons penetrate gate oxide layer 22 and begin accumulating on floating gate 24 due to the relatively positive potential on floating gate 24 with respect to drain region 18.
The potential on floating gate 24 is defined by the voltages which are coupled to floating gate 24 from well 14, source region 16, and drain region 18, and the surface area of floating gate 24 that is formed over these regions. Thus, since floating gate 24 is only marginally formed over source and drain regions 16 and 18, the potential on floating gate 24 is primarily determined by the voltage applied to well 14.
Therefore, when ground is applied to well 14 (and source region 16), and the negative breakdown voltage is applied to drain region 18 during programming, the potential on floating gate 24 is slightly less than ground which, in turn, is relatively positive with respect to the negative breakdown voltage applied to drain region 18.
(If a positive breakdown voltage is applied to well 14 and ground is applied to drain region 18, then floating gate 24 will have a potential slightly less than the positive breakdown voltage which, in turn, is positive with respect to ground which is applied to drain region 18).
Transistor 10 is read by applying ground to well 14 and source region 16, and a read voltage to drain region 18. If transistor 10 has been programmed, the negative charge on floating gate 24 causes channel region 20 to invert (which inversion is permanent as long as the negative charge remains on floating gate 24). As a result, the read biasing voltages applied to source and drain regions 16 and 18 cause a current to flow from drain region 18 to source region 16.
On the other hand, if transistor 10 has not been programmed, the slight negative charge which is coupled to floating gate 24 is insufficient to invert channel region 20. As a result, channel region 20 remains in accumulation. Thus, when the read biasing voltages are applied to source and drain regions 16 and 18, no current is able to flow.
Memory transistor 10 is erased by irradiating transistor 10 with ultraviolet (UV) light to remove the electrons. The UV light increases the energy of the electrons which, in turn, allows the electrons to penetrate the surrounding layers of oxide.
Thus, the Frohmann-Bentchkowsky transistor utilizes a p-channel MOS-type device to inject electrons onto the floating gate (as contrasted with more recent EPROM devices that use an n-channel MOS-type device to inject electrons onto the floating gate).
Although some of the first EPROMs sold by Intel.TM. were based on the Frohmann-Bentchkowsky transistor, the transistor was soon replaced with alternate structures, and has since fallen into relative obscurity.
The parent invention disclosed that by forming a Frohmann-Bentchkowsky memory transistor to have a physical gate length which is less than the physical gate length of a CMOS transistor, as defined by a predetermined design rule, the Frohmann-Bentchkowsky memory transistor is programmable with the voltages that are allowed under the predetermined design rule.
The parent invention, however, did not disclose the use of multiple Frohmann-Bentchkowsky memory transistors. Since numerous instances exist where more than a single EPROM device is required, there is a need for a memory device that incorporates a large number of Frohmann-Bentchkowsky memory transistors.